The present application relates generally to an improved data processing apparatus and method and more specifically to mechanisms for reducing dynamic random access memory (DRAM) power consumption and improving DRAM performance.
Many modern computing devices use dynamic random access memory (DRAM) structures, such as in a main memory, system memory, cache memory, or other memory structures of the computing device. DRAM is a type of volatile random access memory that stores each bit of data in a separate capacitor within an integrated circuit. Since capacitors leak charge, the information in the DRAM cells eventually fades unless the capacitor charge of the DRAM cells is refreshed periodically. Because of this refresh requirement, DRAM is “dynamic” memory as opposed to static random access memory (SRAM) which is “static.” The advantage of DRAM over SRAM is that it only requires one transistor and a capacitor per bit of data that is stored as opposed to six transistors in an SRAM per bit of data. This allows DRAM to reach very high density.
Refreshing DRAM cells may be performed on a periodic basis, such as at a predetermined refresh interval. The refreshing of DRAM cells may also occur, for example, in response to the reading of data out of the DRAM cells. That is, a typical read of a portion of a DRAM structure involves reading out the data from the DRAM cells, which effectively deletes the contents of the DRAM cells due to the loss of charge from the reading operation, with a subsequent rewriting of the data back into the same DRAM cells. Thus, each read of a DRAM structure involves the sensing of charge in the DRAM cells with a subsequent recharging of the DRAM cells to their previous state by rewriting the data back into the DRAM cells, consuming power and leading to a source of DRAM inefficiency.